The present invention relates to a process suitable for etching small features and patterns in silicon silicide and polycide at a high etch rate. In particular, the present invention is directed to a process using iodine-containing gas and bromine-containing gas for reproducibly forming high aspect ratio openings such as grooves, holes and trenches in single crystal silicon.
Recently, integrated circuit (IC) technology has advanced from large scale integration (LSI) to very large scale integration (VLSI) and is projected to grow to ultra-large integration (ULSI) over the next several years. This advancement in monolithic circuit integration has been made possible by improvements in the manufacturing equipment as well as in the materials and methods used in processing semiconductor wafers into IC chips. However, at least four factors impose increasingly stringent requirements on the basic integrated circuit fabrication steps of masking, film formation, doping and etching and on technologies such as dielectric isolation. These factors are, first, the incorporation into IC chips of increasingly complex devices and circuits; second, the use of greater device densities and smaller minimum feature sizes and smaller separations; third, the use of composite conductor layers such as the suicides of tungsten, tantalum, titanium and molybdenum and polycides (silicide over polysilicon) and, fourth, the use of the third wafer dimension, depth, as well as the surface area for example, to form buried or trench capacitors.
The ability to etch narrow, deep, high aspect ratio trenches is crucial to the formation of buried or pit capacitors. Also, single crystal silicon trench isolation is used increasingly by semiconductor research scientists as an alternative to other device isolation technologies. The trench dielectric isolation technique potentially has a number of advantages, including relatively small surface area requirements, the potential for small width-to-depth ratios, and vertical wall profiles.
Another important advantage of the trench technology is its relative process simplicity. To create a buried capacitor or a dielectric isolation structure using trench technology involves reactive ion etching (RIE) a groove into the single crystal silicon substrate, oxidizing the sidewalls of the groove or trench, filling the groove with oxide dielectric or polysilicon and planarizing the surface. It should be noted that the single crystal silicon material can be either an epitaxial layer or a bulk silicon substrate or a composite of both.
Achieving the optimum single crystal silicon etch requires reproducible control of a number of factors including: the wall profile; bottom profile; masking material selectivity; etch rate uniformity; and line width loss. There are a number of process variables, of course, such as the choice of chemistry, pressure, flow rates, etc. The complicated effects of these interdependent variables make it difficult to achieve reproducible control of the trench profile, etch rate and other characteristics, particularly in narrow deep trenches, when the width, w, is less than about one micrometer and/or the depth, d, is greater than about five micrometers.
Referring to FIG. 1, the best trench profile for many isolation and buried capacitor applications is the U-shaped profile, which is designated generally by the reference numeral 10. The U-profile 10 is formed in the silicon substrate 11 by parallel vertical sidewalls 12--12 and a bottom 13 that has rounded edges or corners 14--14. The ability to etch vertical sidewalls 12--12 is necessary for dimensional control and a high aspect ratio, particularly at very small trench widths, w, and deep trench depths, d (aspect ratio A.sub.r =d/w). The U-shaped bottom 13 with rounded edges 14--14 reduces oxidation-induced stress.
Some of the potentially undesirable profiles that can result from the choice of chemistry and other operating parameters are illustrated schematically in FIGS. 2-5.
FIG. 2 depicts a trench 15 having generally vertical sidewalls 16--16. However, the processing parameters have produced sharp corners 17--17 in trench bottom 18. Stress builds up in such sharp corners during cooling and can cause silicon crystal dislocations that promote current leakage and cracking. This condition also reduces the maximum field strength of buried vertical capacitors.
Another non-rounded trench bottom profile is shown in FIG. 3. Here, trench 20 has substantially vertical sidewalls 21--21, but the bottom edges or corners 22--22 are even more sharply angled than the edges 17--17, FIG. 2. The phenomenon and geometry depicted in FIG. 3, that is, the sharply angled edges 22--22 and convex bottom 23 are termed "trenching".
Still another non-rounded trench bottom profile is shown in FIG. 4, where the non-vertical etch has produced a V-shaped trench 25 having angled sidewalls 26--26 which form a single sharp bottom edge 27.
Finally, FIG. 5 depicts the "bowing" phenomenon which is frequently associated with high rate etching processes. That is, the trench 30 depicted in FIG. 5 has concave or bowed sidewalls 31--31. The primary shortcomings of the bowed profile are an increase in the lateral area of the trench, a corresponding reduction in the area available for active devices, and reduced device densities.
The trench profiles shown in FIGS. 2-5 may be useful in certain applications. For example, although the V-shaped profile 25 requires a greater opening, w, for a given depth, d, than the vertical profiles and, thus, occupies larger wafer surface area, the V-profile can be used to form buried vertical capacitors. However, in general, the U-shaped profile 10 with its rounded bottom and low stress is greatly preferred. As a consequence, it is desirable that any etch process be able to reproduce the U-shaped trench profile 10 as required and to form other profiles such as the V profile 25, if at all, only by choice.
Still another consideration, or problem, associated with narrow trenches is the tendency of the etch rate to decrease as the magnitude of the depth, d, increases relative to that of the opening dimension, w. For an etch reaction to proceed, the reaction product must desorb from the etch surface so that reactant species can adsorb onto the newly exposed area. Typically, as trench opening dimensions, w, become smaller, the local etch rates decrease due to the crowding of competing reaction components.
"Black silicon" is another prevalent etch problem. This condition is caused by the presence of surface contaminants such as residual oxides, which act as localized etch masks. The areas beneath these micromasks are not etched away until the contaminants are completely eroded and, as a consequence, the bottom of the finished trench substrate develops a rough, light-scattering dark surface appearance that is responsible for the name black silicon.
The formation of black silicon is not an insurmountable problem when using fluorinated process chemistries. However, fluorinated chemistries frequently use photoresist as the masking material. Because the selectivity of silicon to resist is only about 3:1, etch depths are limited to about three micrometers using a one micrometer-thick resist mask and fluorinated gas chemistry. Fluorinated chemistries also have other crucial problems which limit their ability to etch narrow deep grooves, including undercutting beneath the mask and the proximity effect (different etch rates for different feature geometries in a wafer).
Chlorinated gas etchant species and oxide masking material are being used to etch deep trenches. However, the otherwise desirable etching characteristics of chlorinated gas (etch anisotropy and high single crystal silicon selectivity to silicon oxide) impart an undesirable effectiveness to the oxide micromasks and thus create black silicon during the etch.
Moreover, it is very difficult to prevent bowing (FIG. 5) when using chlorinated gas chemistry to etch at a high rate (22 5,000 Angstroms/minute). Also, the bottom profile is depth-dependent. That is, it is very difficult to obtain the desired rounded bottom profile (FIG. 1) in deep trenches. Finally, when using chlorinated gas chemistry, aspect ratios are limited to about 10:1 for geometries (openings, w) larger than about one micron and to only about 5:1 for geometries smaller than one micron.
One exception (a chlorinated gas chemistry etch which avoids problems such as black silicon), is disclosed in commonly assigned, allowed co-pending patent application Ser. No. 764,981, entitled "Process for Etching Single Crystal Silicon", filed Aug. 12, 1985, now abandoned in the name of David Wang et al ("Wang patent application"), which is incorporated herein by reference in its entirety. The referenced Wang patent application discloses a single crystal silicon etch in which a chlorinated etching gas doped with BCl.sub.3 is adapted for etching relatively narrow, U-shaped trenches 15-20 microns deep without the occurrence of trenching, bowing or black silicon.
In general, however, the above-discussed limitations still apply to the use of fluorinated or chlorinated gas chemistries. That is, fluorinated chemistry typically is accompanied by undercutting and the proximity effect and is limited to the formation of relatively wide shallow grooves or trenches. Chlorinated gas chemistry has profile control problems, is subject to phenomena such as black silicon, and may be limited to relatively large geometries and batch etching systems. Also, such conventional processes provide maximum etch rates of about only 400 Angstroms/minute, which is too low to provide adequate throughput in single wafer etchers and, thus, prevents the industry taking full advantage of the single wafer etcher's potential for etch uniformity.